INTERRUPT CONTROL

Interrupts

Virtually all computers provide a mechanism by which other modules ( I / O, memory ) may interrupt the normal processing of the CPU. Interrupts are provided primarily as a way to improve processing efficiency. For example, most external devices are much slower than the processor. Suppose that the processor is transferring data to a printer using the instruction cycle scheme of the figure shown below,

After each write operation, the processor will have to pause and remain idle until the printer catches up. The
length of this pause can be on the order of many hundreds or even thousands of instruction cycles that do not involve
memory.

Clearly this is a wasteful use of the processor. With interrupts, the processor can be engaged in executing other instructions while an I / O operation is in progress.

There are four most common classes of interrupts:

1) Program - Generated by some condition that occur as a result of an instruction execution, eg. division by zero

2)    Timer        -    Generated by a timer within the processor. This allows the OS to perform certain functions on
                                       a regular basis
3)    I / O           -    Generated by an I / O controller, to signal normal completion of an operation or to signal a variety
                               of error conditions.
4)    Hardware -    Generated by a failure such as power afilure or memory parity error.
         failure

Interrupt in 8085

The 8085 has 5 interrupt inputs which are INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP. Each of the three RESTART inputs, 5.5, 6.5, 7.5 has a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable. The three maskable interrupts cause the internal execution of RESTART (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of the state of the interrupt enable or masks.

There are two different types of inputs in the restart interrupts. RST 5.5, and RST 6.5 are high level-sensitive like INTR and are recognized with the same timing as INTR. RST 7.5 is rising edge-sensitive.

For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request (a normally high level signal with a low going pulse is reccomended for highest system noise immunity). The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically. This flip-flop may also be reset by using the SIM instruction or by issuing a RESET IN to the 8085. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out.

The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows :

                                                       TRAP      -    Highest Priority
                                             RST 7.5   -    Second Highest
                                             RST 6.5   -    Third Highest
                                             RST 5.5   -    Fourth Highest
                                             INTR.      -    Lowest Priority

This priority scheme does not take into accountthe priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupts are re-enabled before the end of the RST 7.5 routine.

The TRAP interrupt is useful for catastrophic evants such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the higest priority. It is not affected by any flag or mask. The TRAPinput is both edge and level sensitive. The TRAP input must go hig and must remain high until it is acknowledged. It will not be recognized again until it goes low and hig again. This avoids any false triggering due to noise or logic glitches.